The present invention relates to a bus structure, and, more particularly, to a bidirectional bus structure that can selectively function as an interconnect routing resource.
A programmable logic device (xe2x80x9cPLDxe2x80x9d) is customized in its package to provide particular, user-defined logic functions. In a typical PLD, a programmable interconnect (also called general interconnect) connects various programmable elements of the PLD, such as logic blocks or input/output blocks, to implement those logic functions. The general interconnect includes many routing resources, such as buses, to efficiently provide the necessary signals to the elements of the PLD.
Bus structures in PLDs are well known in the art. For example, illustrative bus structures are described in U.S. Pat. Nos. 5,677,638, 5,847,580, and 5,936,424.
FIG. 1 shows a prior art bidirectional multiplexer chain 100 in a simplified circuit diagram. Note that only one link of the xe2x80x9cchainxe2x80x9d is shown. The complete chain includes N number of links, where N is typically in the tens or hundreds. Thus, lines 112 and 113 in a first link are connected to lines 111 and 114 in a second, adjoining link, respectively. Bidirectional multiplexer chain 100 includes a multiplexer 101 which selectively transfers a signal on line 113 or line 110 to line 114. This propagation direction is arbitrarily designated as East. In contrast, a multiplexer 102 selectively transfers a signal on line 111 or line 110 to line 112. This propagation direction is arbitrarily designated as West.
Line 110 is coupled to a bus driver 103, which is typically a look-up table or a flip-flop in a PLD. The pair of multiplexers within each link of bidirectional multiplexer chain 100, such as multiplexers 101 and 102, are controlled by the same control signal, dsel. Control signal dsel is typically provided by a combination of configuration memory cells and user select signals.
Thus, depending on the respective control signal dsel, each multiplexer 101/102 within a link can selectively get its input signal from bus driver 103 or from the adjacent multiplexer in its respective path (i.e., the East path or the West path). When multiplexers 101 and 102 are programmed to transfer the signal from bus driver 103, the multiplexers are said to be in the inject mode, and when the multiplexers are programmed to transfer the signal from multiplexers in adjacent links, the multiplexers are said to be in the bypass mode.
An OR gate 104 receives its input signals from multiplexers 101 and 102 and provides its output signal to general interconnect 105. To be used as an interconnect routing resource, one set of multiplexers 101 and 102 drives a signal from their respective driver 103 onto the East and West paths (the inject mode). All other sets of multiplexers 101 and 102 in bidirectional multiplexer chain 100 are programmed to propagate signals from adjacent links (the bypass mode). Typically, many OR gates 104, also called tap points, are placed along the length of bidirectional multiplexer chain 100, thereby ensuring that the propagated signal is easily accessible to nearby logic via general interconnect 105. In this manner, bidirectional multiplexer chain 100 provides a large number of drivers while maintaining switching speed and flexibility in routability.
When bidirectional multiplexer chain 100 is used as an interconnect resource, however, both the East and the West paths are xe2x80x9cdedicatedxe2x80x9d to propagating a single signal. No other signal can use bidirectional multiplexer chain 100 without causing signal contention.
One of the objects of the invention is to provide a flexible, bi-directional multiplexer chain that allows multiple signals to use the multiplexer chain as an alternate interconnect routing resource.
A bus structure is described. The bus structure includes a bi-directional multiplexer chain. Each link of the chain includes a first multiplexer propagating signals in a first direction and a second multiplexer propagating signals in a second direction. The bus structure also includes a circuit for selectively combining output signals of the first and second multiplexers and selectively propagating an output signal of one of first and second multiplexers.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follow below.